In the prior art, a useful layout of MOS random access memories at a major surface of a semiconductive silicon body comprises a pair of complementary two-dimensional arrays (A, A) of MOS capacitive memory cells, with a one dimensional (linear) array of flip-flop sense amplifier detectors situated betwee the arrays. More specifically, each such two-dimensional memory array comprises a rectangular matrix of N rows ("bit" lines) and M columns ("word" lines)--that is, a total of 2MN memory cells for the pair of arrays. A separate storage cell is located at each crosspoint of a bit line and a word line. Each of the flip-flop detectors, a total of N in number, connects a corresponding bit line (B.sub.j, with j=1, 2, 3 . . . N; i.e. B.sub.1, B.sub.2, B.sub.3, . . . B.sub.N) in one of the rectangular memory arrays (A) with a complementary bit line (B.sub.j) in the other of the memory arrays (A). Typically, each cell in each memory array (A, A) comprises an MOS storage capacitor (C.sub.jk, C.sub.jk, respectively, with k=1, 2, 3, . . . M) connected at the corresponding crosspoint of the j'th bit line (B.sub.j) and the k'th word line. Each such storage capacitor is electrically accessed through a separate MOS field effect transistor acting as an accessing switch.
During operation, each such capacitor can store a quantity of electrical charge suitable for representing an information state of the cell corresponding to a "full" cell or binary digital "1" state, or can store no electrical charge corresponding to an "empty" cell or binary digital "0" state. The determination as to which of the two possible states ("1" vs. "0") the cell represents at any time can be made by flip-flop detector (FF.sub.j), one of whose terminals is connected to the same bit line (B.sub.j) as that to which the capacitor is connected and the other of whose terminals is connected to a comparison or reference cell. Typically, the reference cell furnishes the flip-flop detector a reference voltage level (.nu..sub.m) substantially midway between the voltages (.nu..sub.1 and .nu..sub.0) furnished by "full" and "empty" cells, that is, midway between "1" and "0". Thus, each flip-flop detector (FF.sub.j) services all capacitive memory cells (C.sub.jk and C.sub.jk) on the same bit line and its complement (B.sub.j and B.sub.j), a total of 2M storage capacitors (C.sub.jk and C.sub.jk). More specifically, each flip-flop detector (FF.sub.j) performs the detection operation by means of selective access connection of one of the storage capacitors (C.sub.jk or C.sub.jk) through the one corresponding bit line (B.sub.j or B.sub.j) and the simultaneous connection of the corresponding complementary bit line (B.sub.j or B.sub.j) to a corresponding reference cell which furnishes a suitable intermediate reference voltage for comparison purposes.
During the detection operation, the flip-flops are energized by a common latching pulse (common to all flip-flops), whereby each flip-flop (FF.sub.j) (acting as a sense amplifier detector) goes into one of two possible states depending upon whether the voltage on the corresponding bit line (B.sub.j or B.sub.j) is greater vs. less than the voltage on the corresponding complementary bit line (B.sub.j or B.sub.j) and hence depending upon whether the voltage across the corresponding accessed storage capacitor (C.sub.jk or C.sub.jk) is greater vs. less than the voltage across the reference call, that is, depending upon whether the corresponding accessed storage capacitor (C.sub.jk or C.sub.jk) is in the digital "1" vs. digital "0" state. Typically, each such flip-flop (FF.sub.j) comprises a pair of cross-coupled transistors (Q.sub.j, Q.sub.j) feeding a pair of load transistors, whereby, when the flip-flops are energized by the latching pulse, one of the cross-coupled transistors (Q.sub.j, Q.sub.j) in a given flip-flop is in the "on" state and the other is in the "off" state depending upon whether the accessed storage capacitor (C.sub.jk or C.sub.jk) is in the "1" or "0" state, and thus the one or the other load transistor will carry a large vs. small current. These load transistors are typically all energized (turned "on") by a pulse clock (PC.sub.2) voltage applied to their gate electrodes after the latching pulse commences. In this way, each flip-flop (FF.sub.j) amplifies the voltage difference, (.nu..sub.1 -.nu..sub.n) or (.nu..sub.2 -.nu..sub.n), between the voltage across the corresponding accessed storage capacitor (.nu..sub.1 for a full cell, .nu..sub.0 for an empty cell) and the intermediate reference voltage (.nu..sub.n). This amplified voltage difference thus also appears across the corresponding bit line pair (B.sub.j, B.sub.j) to which the flip-flop (FF.sub.j) is connected.
Ordinarily, memory arrays in the semiconductor art are fabricated with three types or planes of electrical interconnections. One such plane of interconnection is afforded by impurity-diffused conductive lines, running along the surface of the semiconductive silicon body; the other two planes of interconnections are afforded by conductive lines defined by two separate levels of metallization located above, and insulated from, the surface of the silicon body. Typically, a lower metallization plane ("first level") is defined by polycrystalline silicon metallization lines and a higher metallization plane ("second level") is defined by aluminum metallization lines.
As the art has progressed, it has become possible in this type of metallization technology ("two-level MOS metallization") to arrange an array of charge storage cells (FIGS. 6 and 9), including storage capacitors (C.sub.jk, C.sub.jk) plus accessing switches (M.sub.jk, M.sub.jk), together with the bit lines (B.sub.j, B.sub.j), in a compact configuration which occupies a transverse or lateral space having a width (in the direction transverse to the bit line direction) of as little as twice the minimum feature size (f) per cell, that is, a distance (2f) equal to twice the width of a minimum-width metallization line, or, more nearly precisely, a distance equal to the width of such a metallization line plus the width of a minimum-width gap between successive metallization lines; so that the entire array of memory cells together with the bit lines fits in a lateral space of 2Nf, or 2N times the minimum feature size. However, each flip-flop contains a pair of cross-connected transistors; and each transistor requires at least a source region, a gate region, and a drain region (i.e., at least three minimum features). Therefore, a straightforward two-level metallization arrangement or layout of N flip-flops together with required cross-connections of transistors in each pair plus interconnections to the corresponding bit lines (B.sub.j, B.sub.j) would not result in a desired minimum geometry configuration of a total of but 2Nf or 2N feature sizes (measured in the transverse direction) for the entire array of the N flip-flops; rather, a transverse space of at least 3Nf or 3N feature sizes would be required to accommodate the flip-flops; thus, undesirable fanning-out of the bit lines would be required in order to connect them to the flip-flops--that is, an added semiconductor surface area requirement of the order of N.sup.2 f (quadratic in N) precious semiconductor area. Therefore, it would be desirable to have a corresponding two-level metallization minimum geometry configuration for the flip-flop detectors, that is, an integrated circuit arrangement of N flip-flops which occupies a lateral space of only 2Nf, or 2N times the minimum feature size, so that the entire array of N flip-flops can fit within the same total amount of lateral space as that required for the memory cells. At the same time, it is important that the parasitic capacitance of each bit line (B.sub.j) with respect to the flip-flop latching terminal be the same as that of its complement (B.sub.j), in order to afford proper balance in the detection process.